The present invention concerns an integrated shift register with very low power consumption. Such a register is particularly well suited, though this does not constitute its only field of application, to the construction of a frequency divider circuit usable in any type of small-sized portable device, powered by a battery which is required to ensure the unit's supply with a life time of up to several years. As is known, the problem of energy consumption occurs most acutely when the frequency to be divided is high, even a few MHz, as is the case, for example, in high chronometric performance watches.
Attempts have been made to reduce energy consumption in frequency dividers by using C-MOS integrated binary circuits. Most quartz watches are now equipped with such circuits. In this instance, consumption is essentially determined by the charging and discharging of capacitors presented by each stage of the shift register and with the periodicity of its output signal. Each stage's consumption is consequently proportional to the value of its capacitors and to the frequency of its output signal. For a high frequency quartz watch, then, it is consequently the first stages, that is to say, those dividing the highest frequencies, which are determinative of the power consumption of the electronics. In order to lower the capacitances of these stages, various manufacturing techniques, such as those known by the name of Si-gate or SOS (Silicon on sapphire) have been used. However, to keep power consumption within acceptable limits, the dimensions of the integrated circuits have to be reduced to such a point that, in the current state of the art, the cost of their manufacture becomes prohibitive.
High frequency dividers with a large part of their capacitors forming part of a resonant circuit have also been proposed to lower power consumption. A system of this type, for example, is described in Swiss Pat. No. 558,111. In this instance, the energy stored periodically in the capacitors is recovered. The system makes use of a shift register of a known type, realized in integrated form and designated an IGFET (insulated gate FET) bucket brigade register. This register is ring connected and a single charge packet is transferred from one cell to the other. Each cell comprises firstly two IGFET's which are connected in series, and two capacitors connected between the respective transistor control electrodes and drains. The control electrodes are connected alternately to two lines supplied by a push-pull quartz oscillator supplying alternating voltages in phase opposition. Means also are provided to bias the crystalline substrate in which the circuits are integrated. The register cell presents a low load for the oscillator and the reactive current due to this capacitance causes a very small loss in the quartz. The largest part of the power which the oscillator has to supply is that dissipated in the transistor through which the transfer of the charge from one stage (half-cell) to the other is made.
The mode of operation of the shift register described above (and a detailed explanation of which is to be found in the article of C. N. Berglund et al, "Fabrication and Performance Considerations of Charge-Transfer Dynamic Shift Registers," Bell System Technical Journal, Vol. 51, No. 3, March 1972) is such that the current goes through the transistor for about 1/4 period and the source-drain voltage of the latter changes during this time from practically the value V.sub.P to 0, V.sub.P being the peak-to-peak value of the phase supply voltage supplied by the oscillator. Consequently, the power supplied by the oscillator expressed by the general relation: ##EQU1## in which i.sub.D (t) and v.sub.SD (t) are instantaneous values respectively of the drain current and of the source-drain voltage of the transistor, T being the oscillation period, then becomes: EQU P.sub.T =(V.sub.p +v.sub.m).sup.2 .multidot.c.multidot.f.
In this expression, C is the capacitance, associated with the transistor, f is the oscillator frequency, and v.sub.m represents the average control voltage which exceeds the transistor threshold voltage. The voltage v.sub.m is normally a few tenths of volt, while v.sub.p is a few volts.
By taking a typical example with the values:
V.sub.P =2 V, v.sub.m =0.3 V, C+0.1 p F, and f=4.2 MHz, a value of 2.2 .mu.W is obtained for P.sub.T.
The power supplied by the oscillator is consequently relatively high because of the high voltage necessary for the transfer of the charge packet from one cell of the register to the other.